1. Field of the Invention
The present invention relates to a circuit for decoupling conduction lines from each other. More specifically, the invention relates to a circuit for decoupling conduction lines from each other, which circuit includes at least one pass gate element having conduction terminals connected to the conduction lines and having at least one control terminal.
2. Description of the Art
As it is well known, two conduction lines of an electronic circuit are normally connected together through a decoupling circuit 10 as shown in FIG. 1 that comprises essentially a pass gate element.
In particular, the decoupling circuit 10 includes a pass gate decoupling transistor operative to connect the lines to each other allowing a signal to go through when in the xe2x80x98onxe2x80x99 state. It is operative to isolate the lines from each other and prevent the signal from going through when in the xe2x80x98offxe2x80x99 state.
As shown schematically in FIG. 1, first L1 and second L2 conduction lines are connected to each other through a pass gate decoupling circuit 10, essentially comprising a decoupling transistor N1.
The decoupling transistor N1 has its conduction terminals respectively connected to said conduction lines L1 and L2, and has a control or gate terminal connected to an input inverter I1. The decoupling transistor N1 may be a pass gate MOS transistor of the N or the P type, for example.
It should be noted that, for example when enhancement transistors are used, the decoupling condition of the conduction lines L1 and L2 (transistor xe2x80x98offxe2x80x99) is obtained by equalizing the gate terminal voltage and the bulk terminal voltage.
In this way, so long as the voltage signals presented on the two conduction lines L1 and L2 connected to the conduction terminals are above a ground reference level GND for an N-type decoupling transistor N1, or below a supply level Vdd for a P-type decoupling transistor, as it is usually happens the case in most circuits, the decoupling transistor N1 will actually be xe2x80x98offxe2x80x99 and the conduction lines L1, L2 properly decoupled.
On the other hand, if the voltage signals at the conduction terminals lie outside the above ranges, i.e., are below the ground reference level GND for an N-type decoupling transistor N1, or above the supply level Vdd for a P-type decoupling transistor, the decoupling transistor N1 might fail to go xe2x80x98offxe2x80x99, and the conduction lines L1, L2 might become improperly coupled.
Such abnormal operating condition are commonly known as disturbed conditions, and the voltage or current signals that originate them will be referred to as disturbing signals hereinafter.
In particular, in the instance of an enhancement decoupling transistor N1 of the N type, having its bulk terminal and gate terminal connected to a ground reference GND and, accordingly, being in a closed channel condition, the decoupling transistor N1 is turned off when the voltages at the conduction terminals are positive voltages.
In the event of one of the conduction terminals, e.g., the drain terminal, being at a lower voltage than the ground reference voltage GND, the voltage Vgs between the further conduction terminal, e.g., the source terminal, and the gate terminal might exceed the threshold voltage of the transistor, so that the latter shows out to be inexpediently on.
Thus, under the conditions outlined hereinabove, a decoupling transistor N1 of the N type is ineffective for the purpose of isolating the two conduction lines L1 and L2 from each other, and would rather allow an objectionable signal through.
This is congruously true for a P-type transistor, whenever the voltage at one of its conduction, source or drain terminals, is higher than the supply reference Vdd used here for biasing its bulk and gate terminals.
The particular instance of an N-type pass gate transistor will be considered hereinafter, it being understood that the same considerations are also true for a P-type transistor, where the terms are consistently substituted with their duals (transistor Nch less than -- greater than  transistor Pch, reference GND  less than -- greater than  reference Vdd, higher than  less than -- greater than  lower than, etc.), as it is obvious to a skilled person in the art.
The aforementioned disturbing signals appear in various operating condition of electronic circuits, as exemplified here below:
1) Inside a generic electronic circuit:
a. when two internal circuit nodes have different internal ground references (Vcc), because of resistances internal of the electronic circuit; and
b. when a floating node is driven by capacitive effect.
2) In an I/O interface circuit on nodes that are connected to pads external of the electronic circuit:
a. when voltage undershoots or overshoots occur because of inductive effects; and
b. when outside of the I/O interface circuit a signal below the ground reference (or likewise, above the supply reference Vdd) is.
Electrostatic discharges (ESD) will not further be taken into account because the circuitry is assumed to incorporate adequate ESD protection structures.
The underlying technical problem addressed by the disclosed embodiments of this invention is to provide satisfactory isolation between conduction lines that are interconnected by a pass gate element, despite the presence of a disturbing signal on the lines, so as to avoid the malfunction condition of prior circuits.
The principle on which the embodiments of this invention stand is the one of connecting, in a circuit for decoupling conduction lines that are interconnected through a pass gate element, a protection circuit suitable to avoid the propagation of a disturbing signal over the lines, so as to provide the right turn-off condition for the pass gate element, meaning the right isolation condition of the conduction lines.
Based on the above principle, the technical problem is solved by a decoupling circuit for decoupling conduction lines from each other, the circuit having at least pass one gate element with conduction terminals connected to the conduction lines and at least one control terminal; and at least one protection circuit inserted between the control terminal and the at least one conduction line, the protection circuit including at least one protection transistor connected to the control terminal and to the at least one of the conduction lines and configured to take in any disturbing signal passing through the pass gate element to properly decouple the conduction lines from each other on the occurrence of a disturbing condition resulting from the disturbing signal.
In accordance with another aspect of the invention, a decoupling circuit is provided that has a decoupling transistor with first and second conduction terminals connected to first and second conduction lines, and a control terminal coupled to an inverter, and a protection circuit coupled to the inverter and the second conduction line, the protection circuit including a pull-up transistor having a first terminal coupled to a voltage source and a second terminal coupled to the second conduction line via a second decoupling transistor, and a control terminal coupled to the inverter, the second decoupling transistor having a first terminal coupled to the second terminal of the pull up transistor, a second terminal coupled to the second conduction line, and a control terminal coupled to the inverter.
In accordance with yet another aspect of the present invention, a decoupling circuit is provided that includes a decoupling transistor having first and second conduction terminals coupled to first and second conduction lines, respectively, a control terminal coupled to the output of an inverter, and a protection circuit comprising a protection transistor having a first conduction terminal coupled to the first conduction line, a second conduction terminal coupled to the output of the inverter, and a control terminal coupled to a ground reference potential.
In accordance with yet a further aspect of the present invention, a decoupling circuit is provided that includes a decoupling transistor having first and second conduction terminals coupled to first and second conduction lines, respectively, and a control terminal coupled to the output of an inverter, and further including a first protection circuit coupled between the second conduction line and the decoupling transistor and further coupled to the output of the inverter, and a second protection circuit coupled to the first conduction line and to the output of the inverter, the first and second protection circuits configured as described above.